Memory systems are often times arranged in a stub architecture. In such an architecture, memory modules are arranged in parallel as stubs along a common data bus, control/address bus, and clock bus. In order to increase data transmission rates in a memory system having a stub bus architecture, careful control over signal integrity is necessary; signal integrity in turn being affected by the stub load. A stub load behaves on a transmission line as a discontinuous point, which results in signal reflection. Signal reflection due to the stub load deteriorates signal integrity, thereby limiting the overall data transmission rate of the system.
Attempts have been made to suppress the detrimental affect of a stub load by configuring the stub bus according to a stub-series-terminated-logic (SSTL) architecture. However this configuration has a fundamental limit in increasing the data transmission rate because, although the adverse effects of the stub load are mitigated, the load is still included in the configuration.
To overcome the limitations encountered by the stub bus architecture, a short-loop-through (SLT) structure has been proposed. In the SLT bus structure, system components are arranged in series on a signal line. In the case of a memory module, for example, the signal line extends along the motherboard through a module connector to a first side of the module and on to a desired component on the module. The signal line then passes through the module body to a second component on a second face of the module and returns to the motherboard through a second coupling on the module connector. From the first module connector, the signal line extends on the motherboard to a second module connector, to the second module, and so on. Therefore, in the SLT bus structure, there are no discontinuous points due to stub loads, such that signal integrity is enhanced and data transmission rate can therefore be increased. However since two pins are required for each signal, the resulting number of module pins is double the number required by the stub bus structure, which increases system costs. Moreover, the loading of a signal line increases as the number of modules increases, which limits the maximum operable data transmission rate.
To address the limitations encountered in the SLT bus structure, a point-to-point bus structure has been proposed. For example, U.S. Pat. No. 5,742,840, to Hansen, et al. proposes such a structure in FIG. 13. In the point-to-point bus structure, only a single load is driven by a single source, and a discontinuous point such as a stub, does not exist. In this manner, the data transmission rate can be considerably increased. As data is passed from module to module, a complicated clocking scheme is required, as each data transfer between modules may have its own phase relationship and therefore the phase relationship of the clock signals in the read direction and write direction may be different, depending on module position.